The fabrication of integrated circuits involves the creation of several layers of materials that interact in some fashion. One or more of these layers may be patterned so various regions of the layer have different electrical characteristics, which may be interconnected within the layer or to other layers to create electrical components and circuits. These regions may be created by selectively introducing or removing various materials. The patterns that define such regions are often created by lithographic processes. For example, a layer of photoresist material is applied onto a layer overlying a wafer substrate. A photomask (containing clear and opaque areas) is used to selectively expose this photoresist material by a form of radiation, such as ultraviolet light, electrons, or x-rays. Either the photoresist material exposed to the radiation, or that not exposed to the radiation, is removed by the application of a developer. An etch may then be applied to the layer not protected by the remaining resist, and when the resist is removed, the layer overlying the substrate is patterned.
Lithographic processes such as that described above are typically used to transfer patterns from a photomask to a device. As feature sizes on semiconductor devices decrease into the submicron range, there is a need for new lithographic processes, or techniques, to pattern high-density semiconductor devices. Several new lithographic techniques which accomplish this need and have a basis in imprinting and stamping have been proposed. One in particular, Step and Flash Imprint Lithography (SFIL) has been shown to be capable of patterning lines as small as 20 nm.
SFIL templates are typically made by applying a layer of chrome, 10–100 nm thick, on to a transparent quartz plate. A resist layer is applied to the chrome and patterned using either an electron beam or optical exposure system. The resist is then placed in a developer to form patterns on the chrome layer. The resist is used as a mask to etch the chrome layer. The chrome then serves as a hard mask for the etching of the quartz plate. Finally, the chrome is removed, thereby forming a quartz template containing relief images in the quartz.
Overall, SFIL techniques benefit from their unique use of photochemistry, the use of ambient temperatures, and the low pressure required to carry out the SFIL process. During a typical SFIL process, a substrate is coated with an organic planarization layer, and brought into close proximity of a transparent SFIL template, typically comprised of quartz, containing a relief image and coated with a low surface energy material. An ultraviolet or deep ultraviolet sensitive photocurable organic solution is deposited between the template and the coated substrate. Using minimal pressure, the template is brought into contact with the substrate, and more particularly the photocurable organic layer. Next, the organic layer is cured, or crosslinked, at room temperature by illuminating through the template. The light source typically uses ultraviolet radiation. A range of wavelengths (150 nm–500 nm) is possible, however, depending upon the transmissive properties of the template and photosensitivity of the photocurable organic. The template is next separated from the substrate and the organic layer, leaving behind an organic replica of the template relief on the planarization layer. This pattern is then etched with a short halogen break-through, followed by an oxygen reactive ion etch (RIE) to form a high-resolution, high aspect-ratio feature in the organic layer and planarization layer.
The distinction between a lithographic mask and a lithographic template should be noted. A lithographic mask is used as a stencil to impart an aerial image of light into a photoresist material. A lithographic template has a relief image etched into its surface, creating a form or mold. A pattern is defined when a photocurable liquid flows into the relief image and is subsequently cured. The attributes necessary for masks and templates, therefore, are quite different.
SFIL technology has been demonstrated to resolve features as small as 20 nm. As such, a wide variety of feature sizes may be drawn on a single wafer. Certain problems exist though with this SFIL template fabrication methodology as described above. In particular, problems exist with respect to: (i) uniform etching of the quartz template when only a chrome hard mask is utilized; (ii) image distorting charging effects during electron beam patterning of the template; (iii) the effects of charging during scanning electron microscope inspection of the fabricated template; and (iv) the elimination of the detection of false defects during optical or e-beam defect inspection.
Of concern is the fact that quartz is very resistive and prone to charging during e-beam irradiation. Accordingly, there is a desire to include within the template fabrication a transparent conductive coating to eliminate this concern. The inclusion of a transparent conductive coating, or layer, will provide for the elimination of image distorting charging effects during electron beam patterning of the template, elimination of charging effects during scanning electron microscope inspection of the fabricated template, and service as an etch stop barrier layer during oxide patterning. The most convenient transparent conductive material is indium-tin-oxide (ITO), although many other transparent conductive materials providing these benefits can be used. Common deposition techniques for ITO involve heating the substrate to approximately 200° C. during the deposition process. Unfortunately, this produces films which are rough and grainy. This production of a rough and grainy conductive layer will not produce the desired results as described above.
In addition, there exist problems with the electron-beam writing of the template and the inspection of the template subsequent to fabrication. With the inclusion of a conductive layer, charge build-up during electron-beam exposure is avoided. In addition, inspectability is achievable due to the template being comprised of multiple materials. Typical inspection systems use either light (ultraviolet or deep ultraviolet) or electrons to determine feature size and detect unwanted defects on the template. Light-based systems require a difference in reflection or index of refraction between patterned and unpatterned areas of the template to provide good image contrast. Likewise, an electron-based system requires a difference in atomic number between patterned and unpatterned areas of the template. To overcome this problem, multiple materials having either different optical properties or different atomic numbers would allow for inspection, a necessity for sub-100 nm features.
Accordingly, it would be beneficial to provide for a means of eliminating image distorting charging effects during electron beam patterning of the template and eliminate charging effects during scanning electron microscope inspection of the fabricated template.
It is a purpose of the present invention to provide for an improved lithographic template, a method of fabricating the improved lithographic template, and a method for making semiconductor devices with the improved lithographic template in which included is a transparent conductive layer.
It is a purpose of the present invention to provide for an improved lithographic template, a method of fabricating the improved lithographic template, and a method for making semiconductor devices with the improved lithographic template in which elimination of image distorting charging effects during electron beam patterning of the template is achieved.
It is a purpose of the present invention to provide for an improved lithographic template, a method of fabricating the improved lithographic template, and a method for making semiconductor devices with the improved lithographic template in which elimination of charging effects during scanning electron microscope inspection is achieved.
It is yet another purpose of the present invention to provide for an improved lithographic template, a method of fabricating the improved lithographic template, and a method for making semiconductor devices with the improved lithographic template in which improvement in the inspection of sub-micron structures is achieved by eliminating false defects during optical and e-beam defect inspection.